1. Field of the Invention
The present invention relates to electronic semiconductor devices, and, more particularly, to interfaces of silicon-based and III-V-based circuits.
2. Description of the Related Art
Many researchers have investigated growth of semiconductor-device quality gallium arsenide (GaAs) on silicon wafers and fabrication of active devices in the GaAs. Such devices would combine the higher mobility of carriers in GaAs with the greater mechanical strength and thermal conductivity of a silicon substrate. For example, R. Fischer et al, GaAs/AlGaAs Heterojunction Bipolar Transistors on Si Substrates, 1985 IEDM Tech.Dig. 332, report GaAs/AlGaAs heterojunction bipolar transistors grown on silicon substrates and having current gains of .beta.=13 for a 0.2 .mu.m thick base. Similarly, G. Turner et al, Picosecond Photodetector Fabricated in GaAs Layers Grown on Silicon and Silicon On Sapphire Substrates, 1985 IEDM Tech.Dig. 468, report response times of 60 picoseconds for photoconductive detectors fabricated in GaAs on silicon. H. Shichijo et al, GaAs E/D MESFET 1-kbit Static RAM Fabricated on Silicon Substrate, 8 IEEE Elec.Dev.Lett. 121 (1987) reports a static RAM in GaAs on silicon, and H. Tran et al, GaAs/AlGaAs Heterojunction Emitter-Down Bipolar Transistors Fabricated on GaAs-on-Si Substrate, 8 IEEE Elec.Dec.Lett. 50 (1987) reports a vertical heterojunction bipolar transistor in GaAs on silicon. These articles also note that majority carrier devices such as MESFETs fabricated in GaAs on silicon have performance approaching that of homoepitaxial devices; and this has encouraged efforts to integrate GaAs-based optoelectronic and high-frequency devices with high density silicon devices on the same wafer to utilize high-data-rate optical or electrical interconnections, thereby reducing the number of wire interconnections or enhancing system performance through selective use of high speed GaAs devices on silicon VLSI. In order to achieve this goal, however, it will be necessary to develop materials growth and device processing techniques that will permit the coexistance of circuit elements with vastly different fabrication requirements. One of the most promising of these approaches is the patterned growth of GaAs onto a silicon substrate through openings in a protective mask of either silicon nitride (Si.sub.3 N.sub.4) or silicon dioxide (SiO.sub.2). In this scheme, the fabrication of the silicon based devices (which typically require high temperature processing) would be completed prior to the deposition of a protective oxide or nitride overlayer. Single crystal GaAs could then be grown into lithographically defined holes in the overlayer, and GaAs device fabrication would follow.
Previous work has established that epitaxial GaAs can be successfully deposited onto silicon substrates through a patterning mask; see B. Y. Tsaur et al, 41 Appl Phys. Lett. 347 (1982), P. Sheldon et al, 45 Appl. Phys. Lett. 274 (1984), Daniele et al, U.S. Pat. No. 4,587,717, and Betsch et al, U.S. Pat. No. 4,551,394. In addition, the integration of Si and GaAs device structures via this technology has been demonstrated; see H. K. Choi et al, 7 IEEE Elec.Dev.Lett. 241 and 500 (1986); and H. Shichijo et al, Co-Integration of GaAs MESFET and Si CMOS Circuits, 9 IEEE Elec.Dev.Lett. 444 (1988).
The simplest avenue for the patterned growth of GaAs on Si would involve the epitaxial growth of the GaAs onto the original planar silicon surface. However, the final level of the GaAs surface where device fabrication occurs may be several microns above the the level of prefabricated silicon devices. This situation would naturally complicate the interconnect of the two device structures by conventional metallization schemes. Indeed, for integrated circuits with both digital silicon and digital GaAs devices on an underlying silicon substrate, the coplanarity between the surface of the GaAs regions and the surface of the silicon substrate is essential. One method to achieve this coplanarity is by forming recesses in the silicon substrate where the GaAs regions are to be located and then growing a GaAs layer until the surface of the GaAs in the recesses is coplanar with the surface of the silicon substrate outside of the recesses. Typically the recesses will be about two to three microns deep. FIG. 1a illustrates in cross sectional elevation view of a MESFET in a GaAs-filled recess in a silicon substrate connected to a p-channel MOSFET in a n well in the silicon substrate. FIG. 1a is heuristic and does not indicate the interface problem between GaAs circuits and silicon circuits which typically operate at different voltage levels and swings.
Hybrid circuits with GaAs and silicon circuits on seperate substrates which are wired together typically have level translation subcircuits built-in at the input and output of the GaAs circuits to provide compatibility with the silicon circuits. See for example, M. Ino et al, A 1.2 ns GaAs 4 kb Read-Only-Memory Fabricated by 0.5 .mu.m-Gate BP-SAINT, 1987 IEEE GaAs IC Sump. 189; M. Kane, A 1.5 GHz Programmable Divide-by-N GaAs Counter, 23 IEEE J.S.S.C. 480 (1988); G. Schon et al, Fully ECL-Compatible GaAs Standard-Cell Library, 23 IEEE J.S.S.C. 677 (1988); and B. Chappell et al, Fast CMOS ECL Receivers with 100-mV Worst-Case Sensitivity, 23 IEEE J.S.S.C. 61 (1988) which has interfaces for silicon CMOS to silicon ECL. However, these level translation subcircuits must provide high-drive and have large power dissipation.